DCNv4 INT8 patch (Level 1): int8 storage + fp32 arithmetic for SOFIA/MERIDIAN E9

- Add dcnv4_int8_cuda.cu/.h: CUDA kernel (int8 values, fp16 offsets, fp32 interp,
  requantize with value_scale/output_scale)
- Add dcnv4_int8_forward(): inference-only functional wrapper (@no_grad)
- Add DCNv4Strip.forward_int8(): module-level INT8 forward (without_pointwise=True)
- Add scripts/test_dcnv4_int8.py: correctness gate (<=1 LSB, >=99% exact)
  and informational fp16 vs int8 benchmark
- Update README: INT8 API section, updated structure tree, SOFIA/MERIDIAN context

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
This commit is contained in:
2026-06-11 16:19:21 +03:00
parent 1b3206b6a7
commit 71862bbeca
9 changed files with 539 additions and 14 deletions

View File

@@ -59,6 +59,35 @@ def find_spec_bwd(B, H, W, G, C):
n_thread = multiplier * G * C // d_stride
return d_stride, n_thread
@torch.no_grad()
def dcnv4_int8_forward(
value_int8, offset_mask_fp16,
kernel_h, kernel_w, pad_h, pad_w,
group, group_channels,
offset_scale, value_scale, output_scale):
"""Inference-only INT8 DCNv4 (Level 1: int8 storage + fp32 math).
Args:
value_int8: int8 tensor [B, H, W, C], quantized as
real_value = value_int8 * value_scale (per-tensor, symmetric).
offset_mask_fp16: fp16 tensor [B, H, W, padded_offset_dim] — the raw
(real-valued) offsets and masks, NOT quantized.
kernel_h/kernel_w/pad_h/pad_w/group/group_channels/offset_scale:
same semantics as DCNv4Function (stride=1, dilation=1 implied).
value_scale / output_scale: per-tensor quantization scales; the kernel
folds them into a single requantization multiplier
value_scale / output_scale.
Returns:
int8 tensor [B, H, W, C]; real output = result * output_scale.
"""
requant = float(value_scale) / float(output_scale)
return ext.dcnv4_int8_forward(
value_int8, offset_mask_fp16,
kernel_h, kernel_w, 1, 1, pad_h, pad_w, 1, 1,
group, group_channels, float(offset_scale), requant)
class DCNv4Function(Function):
@staticmethod
@custom_fwd