DCNv4 INT8 patch (Level 1): int8 storage + fp32 arithmetic for SOFIA/MERIDIAN E9
- Add dcnv4_int8_cuda.cu/.h: CUDA kernel (int8 values, fp16 offsets, fp32 interp, requantize with value_scale/output_scale) - Add dcnv4_int8_forward(): inference-only functional wrapper (@no_grad) - Add DCNv4Strip.forward_int8(): module-level INT8 forward (without_pointwise=True) - Add scripts/test_dcnv4_int8.py: correctness gate (<=1 LSB, >=99% exact) and informational fp16 vs int8 benchmark - Update README: INT8 API section, updated structure tree, SOFIA/MERIDIAN context Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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@@ -59,6 +59,35 @@ def find_spec_bwd(B, H, W, G, C):
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n_thread = multiplier * G * C // d_stride
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return d_stride, n_thread
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@torch.no_grad()
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def dcnv4_int8_forward(
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value_int8, offset_mask_fp16,
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kernel_h, kernel_w, pad_h, pad_w,
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group, group_channels,
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offset_scale, value_scale, output_scale):
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"""Inference-only INT8 DCNv4 (Level 1: int8 storage + fp32 math).
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Args:
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value_int8: int8 tensor [B, H, W, C], quantized as
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real_value = value_int8 * value_scale (per-tensor, symmetric).
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offset_mask_fp16: fp16 tensor [B, H, W, padded_offset_dim] — the raw
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(real-valued) offsets and masks, NOT quantized.
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kernel_h/kernel_w/pad_h/pad_w/group/group_channels/offset_scale:
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same semantics as DCNv4Function (stride=1, dilation=1 implied).
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value_scale / output_scale: per-tensor quantization scales; the kernel
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folds them into a single requantization multiplier
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value_scale / output_scale.
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Returns:
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int8 tensor [B, H, W, C]; real output = result * output_scale.
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"""
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requant = float(value_scale) / float(output_scale)
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return ext.dcnv4_int8_forward(
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value_int8, offset_mask_fp16,
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kernel_h, kernel_w, 1, 1, pad_h, pad_w, 1, 1,
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group, group_channels, float(offset_scale), requant)
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class DCNv4Function(Function):
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@staticmethod
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@custom_fwd
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